1. Technical Field
The present invention relates to signal processing and more particularly to an apparatus and method for providing signal phase control for an integrated radio receiver or transceiver.
2. Description of the Related Art
An example radio transmission system in a context illustrating the need for signal phase control and, in particular, carrier phase recovery in a receiver will be described. A block diagram of a typical radio transmission system 10 is shown in FIG. 1.
Referring to FIG. 1, a binary data stream (data) is modulated by a modulator 12 to In-phase and Quadrature (IQ) baseband signal vectors (I and Q, respectively) using a modulation such as Binary Phase Shift Keying (BPSK) or Quadrature Phase Shift Keying (QPSK). The baseband IQ signals control the sign and amplitude of two orthogonal radio-frequency carrier components, one cosine and one sine carrier. The IQ baseband signals are mixed, or multiplied, in mixers 14 and 16 with the sine and cosine local oscillator signals in a radio transmitter 15 to convert the baseband modulation to a frequency “ftx” suitable for propagation over a radio channel. A local oscillator LO provides a base signal that is adjusted by a phase shifter or quadrature divider 18 to provide the sine and cosine local oscillator signals.
The signals are summed by summer 20 and amplified by amplifier 22 to be sent over a radio channel 24 using antenna 26.
In the radio channel, the signal undergoes attenuation, phase shift, and time dispersion. The effect of channel time dispersion, though important in practical systems, is here assumed small enough to be ignored. The channel phase shift may fluctuate as a function of time, t, if there is significant relative motion between the transmitter and receiver or moving reflectors in the radio channel.
In a receiver system 25, the received signal from antenna 28 is amplified by amplifier 30, split and mixed using mixers 32 and 36 and phase shifter/quadrature divider 36 with a local oscillator signal of local oscillator LO to convert the signal back to baseband, providing baseband I and Q signals which are scaled and phase-rotated replicas of the transmitted signal vectors. In a practical radio system, the frequency of the local oscillator LO in the receiver, shown as “fRX”, will not be identical to the frequency of the local oscillator LO in the transmitter, “fTX”. This frequency error adds a time varying phase error to the received signal, resulting in a typical rotation of the received I/Q signals around the complex plane at a rate proportional to the difference in frequency between the transmit and receive local oscillators.
This phase rotation presents a problem for the receiver when coherent baseband modulation is used. Coherent baseband modulation, by definition, requires that the phase error of the channel be removed prior to demodulation of the received I and Q signals to an estimate of the transmitted binary information.
A specific example of a common modulation which is sensitive to channel phase error is binary phase-shift keying (BPSK). In this system, binary information might be encoded to a modulation value “+1” for a transmitted data bit value of 1 and a modulation value “−1” for a transmitted data bit value of 0. Due to phase rotation in the channel, the received signal may be rotated by an arbitrary amount, so that the “+1” value shows up at an arbitrary rotated angle from −180 to +180 degrees, preventing proper decoding of the received information unless the phase rotation is corrected. Further, due to frequency error, the phase of the received signal varies with time.
One common method to circumvent the phase error in a radio system is to use non-coherent baseband modulation systems. In this type of modulation, the carrier phase does not need to be recovered in the receiver. The phase error in a typical DBPSK, or Differential Binary Phase-Shift Keyed, non-coherent receiver is removed by subtracting the phase of a previously received symbol from the phase of a currently received symbol. Under the assumption that the channel phase is the same or approximately the same for the two closely spaced channel symbols, the phase error subtracts out, and a decision can be made if the angle between two successive symbols is 0 or 180 degrees.
This detection method, combined with differential data encoding, provides a radio system capable of transmitting information without the need for explicit carrier recovery. Both DBPSK and Differential Quadrature Phase-Shift-Key (DQPSK), which encodes pairs of data bits to a differential phase rotation of 0, 90, −90, or 180 degrees, are examples of non-coherent modulation systems.
The coherent detection of BPSK and QPSK may be advantageous, since coherent detection typically removes 3 dB of noise penalty in the decoder. This noise penalty arises, since subtraction of the phase between two successive symbols multiples the RMS value of the channel phase noise by 1.414, or 3 dB. In addition to sensitivity improvement, coherent detection can make the receiver data demodulator very simple, since all that is needed to decode received symbols is a threshold compared against zero (sometimes called a data slicer) on the I or I and Q outputs of the radio receiver.
This feature enables a radio with IQ channel outputs to connect directly to a high-speed clock-and-data recovery (CDR) device which is commonly used in high-speed I/O Serializer/Deserializer (SerDes) systems to provide multiple-Gb data signals for inter-chip communications. Combined with a 60 GHz radio with carrier phase recovery, these high-speed CDRs/SerDes provide the potential of realizing efficient multiple-Gb 60 GHz wireless data transmission systems.
FIG. 2 shows a well-known method used to find the phase of a BPSK signal in an analog demodulation system 70 including a “Costas” loop 50. The Costas loop 50 is based on a product detector which integrates the frequency of a voltage-controlled oscillator (VCO) to lock the demodulated output to the transmitted channel phase. The receiver outputs I and Q to clock-data-recovery (CDR) circuits 52 and decodes the recovered data using a decoder 54. Using low pass filters 56, the I and Q outputs from receiver 25 are mixed in the Costas loop 50 by mixer 58. The Costas loop 50 includes a loop integrator comprising amplifier 60 and a capacitor 62 to generate a filtered control voltage for the voltage-controlled oscillator.
The Costas loop 50 has several disadvantages for use with an integrated radio IC architecture: 1) it requires an analog VCO, which can potentially consume large amounts of power and die area, in addition to adding un-wanted phase noise to the received signal, 2) it has the potential of false-lock, 3) the lock time of the Costas loop system may be excessive for high-speed time-division multiplex (TDM) based physical-layer (PHY) protocols which are typically used in high-speed wireless data transmission systems, and 4) although the Costas loop 50 can be configured to lock to a QPSK signal, the complexity increase is significant.
Referring to FIG. 3, a second common method used in digital receiver systems to realize coherent detection is to employ analog to digital (A/D) converters 72 to convert the received analog signal (typically the baseband I and Q signals) to digital values and employ a digital signal processor 74 to run digital-signal processing algorithms to acquire to the channel phase and subtract it from the received data symbols prior to making bit decisions.
This approach can address all four disadvantages of the analog Costas loop: the analog VCO is replaced with numerical computations done in the digital domain, false-lock can be detected and corrected using numerical algorithms, lock time can be very fast since no analog settling transients are involved, and demodulation of QPSK or other more complex modulation formats can also be addressed using appropriate digital algorithms well known in the art with minimal increase in analog system complexity.
The introduction of the A/D and digital baseband processing brings its own disadvantages, however, for extremely high data rate systems. The main disadvantage is the need for high speed A/D converters and correspondingly fast digital-signal processing logic for high data (multiple Gb/s) data rates. As an example, a 1 Gsym/sec data transmission system produces 1 Gb/s for BPSK and 2 Gb/s for QPSK and requires two 2 Gsample/sec A/D converters.
These high rate converters and associated digital signal processing logic can increase the complexity and power of the demodulation system significantly compared to a CDR data-slicer based I/O core running at comparable data rates.